1. Field
This disclosure relates generally to an integrated circuit and, more specifically, to techniques for selecting spares to implement a design change in an integrated circuit.
2. Related Art
Traditionally, circuit designers have employed circuit design and synthesis software applications (circuit design tools) to design integrated circuits (chips). Typically, circuit designers specify logical computation based on available inputs, desired outputs, and performance parameters within which a chip is required to perform. A completed chip design is defined by a set of logic components (which are capable of performing various logical functions, such as a single logical operation, for example, an AND function, an OR function, a NOT function, a NAND function, a NOR function, or an XOR function, as well as combinations of logical functions) provided in a netlist. A netlist includes a collection of components (e.g., logic components and other circuit components, such as resistors and capacitors) and an organization of the components that result from a circuit design. A logic circuit that is configured to perform one or more logical operations is commonly referred to as a gate. A gate array is a set of gates arranged in a particular manner.
When an original circuit design is complete, a circuit designer usually tests the circuit design for compliance with design parameters (specifications). For example, design specifications may include timing, gate delay, and slew rate. An original circuit design may contain errors, such as faulty logic, or fail to meet design parameters. For example, a specification may call for processor operation at 2 GHz, when a designed processor only operates correctly at 1.8 GHz. As another example, a logic component within a circuit may have a longer delay than permitted, causing a next cone of logic (i.e., logic components that are grouped together to performing a part of a logical computation) that accepts output from the logic component (as input) to produce an incorrect result.
Typically, circuit design code, which is written in a programming language (e.g., VHDL or Verilog), is used to produce sets of photolithographs, which are photographic images of all layers (i.e., semiconductor and metal layers) in a circuit design. One set of photolithographs that is used to fabricate a chip is usually referred to as a release interface tape A (RIT-A) design, which includes images of non-metallic layers used in forming a chip. Another set of photolithographs that is used to fabricate a chip is usually referred to as a release interface tape B (RIT-B) design, which includes a set of photolithographs that contain images of metallic layers of the chip that connect various circuit components. The RIT-A and RIT-B designs are used together to fabricate a designed circuit.
Occasionally, an error in a circuit design may escape detection until after an original circuit design is completed. When an error in a circuit design has occurred, a circuit designer has had to identify the error, design a logic circuit that corrects the error, and modify the original circuit design to include the logic circuit that corrects the error. The circuit designer has then tested the modified circuit design to ensure the modified circuit design actually corrects the error and meets design parameters. Unfortunately, modification of photolithographs associated with an RIT-A design is generally time-consuming and relatively expensive. As such, circuit designers have generally avoided making modifications to photolithographs included in an RIT-A design to correct an error in an original circuit design. As compared to modifying photolithographs in a RIT-A design, modifying photolithographs in an PIT-B design has generally provided a relatively inexpensive way of making modifications to a circuit design.
In an original circuit design of a chip, circuit designers have typically provided filler cells, which are areas on a chip that includes gates that do not have an assigned function in an original circuit design. That is, the filler cells are not connected in an original RIT-B design. In this manner, when an error occurs, a circuit designer may connect one or more filler cells (or portions of one or more filler cells) in a modified RIT-B design to connect logic components required in a modified circuit design. In general, circuit design tools are also used to produce modified circuit designs, in the form of an original RIT-A design and a modified RIT-B design, based on code that describes the modified circuit design.